dg3535/DG3536 micro foot 10-bump nc 2 no 2 no 1 nc 1 gnd v+ xxx 3535 a1 locator 3535 = example base part number xxx = data/lot traceabiliity code nc 2 no 2 com 1 in 2 1 a 234 b c top view com 2 gnd v+ in 1 nc 1 no 1 in 2 in 1 com 2 com 1 no 2 nc 2 com 1 in 2 1 a 234 b c top view com 2 gnd v+ in 1 no 1 nc 1 dg3535 DG3536 device marking dg3535/DG3536 vishay siliconix new product document number: 72961 s-50130?rev. d, 24-jan-05 www.vishay.com 1 0.25- low-voltage dual spdt analog switch features low voltage operation low on-resistance - r on: 0.25 @ 2.7 v ? 69 db oirr @ 2.7 v, 100 khz micro foot package esd protection >2000 v benefits reduced power consumption high accuracy reduce board space 1.6-v logic compatible high bandwidth applications cellular phones speaker headset switching audio and video signal routing pcmcia cards battery operated systems relay replacement description the dg3535/DG3536 is a sub 1- (0.25 @ 2.7 v ) dual spdt analog switches designed for low voltage applications. the dg3535/DG3536 has on-resistance matching (less than 0.05 @ 2.7 v) and flatness (less than 0.2 @ 2.7 v) that are guaranteed over the entire voltage range. additionally, low logic thresholds makes the dg3535/DG3536 an ideal interface to low voltage dsp control signals. the dg3535/DG3536 has fast switching speed with break-before-make guaranteed. in the on condition, all switching elements conduct equally in both directions. off-isolation and crosstalk is ? 69 db @ 100 khz. the dg3535/DG3536 is built on vishay siliconix?s high-density low voltage cmos process. an eptiaxial layer is built in to prevent latchup. the dg3535/DG3536 contains the additional benefit of 2,000-v esd protection. as a committed partner to the community and the environment, vishay siliconix manufactures this product with the lead (pb)-free device terminations. for micro foot analog switching products manufactured with tin/silver/copper (snagcu) device terminations, the lead (pb)-free ??e1? suffix is being used as a designator. functional block diagram and pin configuration truth table logic nc1 and nc2 no1 and no2 0 on off 1 off on ordering information temp range package part number -40 to 85 c micro foot : 10-bump (4x3, 0.5-mm pitch, 238- m bump height) dg3535db-t5?e1 dg3535db-t1?e1 DG3536db-t5?e1
dg3535/DG3536 vishay siliconix new product www.vishay.com 2 document number: 72961 s-50130?rev. d, 24-jan-05 absolute maximum ratings reference to gnd v+ -0.3 to +6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . in, com, nc, no a -0.3 to (v+ + 0.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current (no, nc, com) 300 ma . . . . . . . . . . . . . . . . . . . . . . . peak current 500 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (pulsed at 1 ms, 10% duty cycle) storage temperature (d suffix) -65 to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . package solder reflow conditions b ir/convection 250 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . esd per method 3015.7 >2 kv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation (packages) c micro foot: 10-bump (4x3 mm) d 457 mw . . . . . . . . . . . . . . . . . . . . . . . . . notes: a. signals on nc, no, or com or in exceeding v+ will be clamped by inter- nal diodes. limit forward diode current to maximum current ratings. b. refer to ipc/jedec (j-std-020b). c. all bumps welded or soldered to pc board. d. derate 5.7 mw/ c above 70 c stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratin gs only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications (v+ = 3 v) test conditions otherwise unless specified limits ? 40 to 85 c parameter symbol v+ = 3 v, 10%, v in = 0.5 or 1.4 v e temp a min b typ c max b unit analog switch analog signal range d v no , v nc , v com full 0 v+ v on-resistance d r on v 27 v v 0 6/1 5 v room full 0.25 0.4 0.5 r on flatness d r on flatness v+ = 2.7 v, v com = 0.6/1.5 v i no , i nc = 100 ma room 0.15 on-resistance match between channels d r ds(on) room 0.05 switch off leakage current i no(off) , i nc(off) v+ = 3.3 v, v no , v nc = 0.3 v/3 v room full ? 2 ? 20 2 20 switch off leakage current i com(off) v+ = 3 . 3 v , v no , v nc = 0 . 3 v/3 v v com = 3 v/0.3 v room full ? 2 ? 20 2 20 na channel-on leakage current i com(on) v+ = 3.3 v, v no , v nc = v com = 0.3 v/3 v room full ? 2 ? 20 2 20 digital control input high v oltage d v inh full 1.4 v input low voltage v inl full 0.5 v input capacitance c in full 10 pf input current i inl or i inh v in = 0 or v+ full 1 1 a dynamic characteristics turn-on time t on v no or v nc = 2 0 v r l = 50 c l = 35 pf room full 52 82 90 turn-off time t off v no or v nc = 2 . 0 v , r l = 5 0 , c l = 3 5 p f room full 43 73 78 ns break-before-make time t d v no or v nc = 2.0 v, r l = 50 , c l = 35 pf full 1 6 charge injection d q inj c l = 1 nf, v gen = 1.5 v, r gen = 0 room 21 pc off-isolation d oirr r l = 50 c l = 5 pf f = 100 khz room ? 69 db crosstalk d x talk r l = 50 , c l = 5 pf, f = 100 khz room ? 69 db n o n c off capacitance d c no(off) room 145 n o , n c off capacitance d c nc(off) v in = 0 or v+ f = 1 mhz room 145 pf channel on capacitance d c no(on) v in = 0 or v+, f = 1 mhz room 406 pf channel-on capacitance d c nc(on) room 406 power supply power supply current i+ v in = 0 or v+ room full 0.001 1.0 1.0 a notes: a. room = 25 c, full = as determined by the operating suffix. b. typical values are for design aid only, not guaranteed nor subject to production testing. c. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data s heet. d. guarantee by design, nor subjected to production test. e. v in = input voltage to perform proper function.
dg3535/DG3536 vishay siliconix new product document number: 72961 s-50130?rev. d, 24-jan-05 www.vishay.com 3 typical characteristics (25 c unless noted) 10 10 k 100 k 10 m 100 1 k 1 m 100 ma 10 ma 1 ma 100 a 10 a 1 a 100 na 1 na 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 supply current vs. input switching frequency input switching frequency (hz) i+ ? supply current (a) r on vs. v com and supply v oltage v com ? analog v oltage (v) t = 25 c i s = 100 ma ? on-resistance ( r on ) r on vs. analog voltage and temperature (nc1) v com ? analog v oltage (v) ? on-resistance ( r on ) ? 300 ? 250 ? 200 ? 150 ? 100 ? 50 0 50 100 150 200 250 300 0.0 0.5 1.0 1.5 2.0 2.5 3.0 leakage vs. analog v oltage v com ? analog v oltage (v) v+ = 3 v ? 60 ? 40 ? 200 20406080100 10 10000 100000 supply current vs. temperature temperature ( c) 100 1000 i+ ? supply current (na) v+ = 3.0 v v in = 0 v ? 60 ? 40 ? 200 20406080100 1 10000 leakage current vs. t emperature temperature ( c) v+ = 3.0 v 100 1000 leakage current (pa) i com(on) i com(off) i no(off) , i nc(off) leakage current (pa) v+ = 3.0 v i com(on) i com(off) i no(off) , i nc(off) v+ = 1.8 v v+ = 2.0 v v+ = 3.0 v i s = 100 ma 85 c 25 c ? 40 c 10 na 10 v+ = 2.7 v v+ = 3.0 v v+ = 3.3 v
dg3535/DG3536 vishay siliconix new product www.vishay.com 4 document number: 72961 s-50130?rev. d, 24-jan-05 typical characteristics (25 c unless noted) ? 300 ? 250 ? 200 ? 150 ? 100 ? 50 0 50 100 150 200 250 300 0.0 0.5 1.0 1.5 2.0 2.5 3.0 charge injection vs. analog voltage v com ? analog v oltage (v) q ? charge injection (pc) 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0123456 switching threshold vs. supply v oltage v+ ? supply voltage (v) ? switching threshold (v) v t 100 k ? 90 10 m 10 ? 70 ? 50 100 m 1 g 1 m insertion loss, off-isolation crosstalk vs. frequency frequency (hz) 0 10 20 30 40 50 60 70 80 90 100 ? 60 ? 40 ? 20 0 20 40 60 80 100 switching time vs. t emperature / t on ? switching t ime (ns) t off t on v+ = 3 v t off v+ = 3 v (db) loss, oirr, x talk ? 30 ? 10 v+ = 3.0 v oirr x talk v+ = 3.0 v r l = 50 temperature ( c) t on v+ = 2 v t off v+ = 2 v loss v+ = 2.0 v test circuits figure 1. switching time switch input c l (includes fixture and stray capacitance) v+ in no or nc c l 35 pf com logic input r l 300 v out gnd v+ 50% 0 v logic input switch output t on t off logic ?1? = switch on logic input waveforms inverted for switches that have the opposite logic sense. 0 v switch output v out v com r l r l r on 0.9 x v out t r 5 ns t f 5 ns v inh v inl
dg3535/DG3536 vishay siliconix new product document number: 72961 s-50130?rev. d, 24-jan-05 www.vishay.com 5 test circuits figure 2. break-before-make interval c l = 1 nf r gen v out com v in = 0 ? v+ in gnd v+ v+ + nc or no figure 3. charge injection c l (includes fixture and stray capacitance) nc v no no v nc 0 v logic input switch output v o v nc = v no 90% t d in com v+ gnd v+ c l 35 pf v o r l 300 v inl v inh t r 5 ns t f 5 ns t d off on on in v out v out q = v out x c l in depends on switch configuration: input polarity determined by sense of switch. figure 4. off-isolation figure 5. channel off/on capacitance nc or no f = 1 mhz in com gnd 0 v, 2.4 v meter hp4192a impedance analyzer or equivalent 10 nf v+ v+ in gnd nc or no 0v, 2.4 v 10 nf com off isolation 20 log v com v no nc r l analyzer v+ v+ com
dg3535/DG3536 vishay siliconix new product www.vishay.com 6 document number: 72961 s-50130?rev. d, 24-jan-05 package outline micro foot: 10-bump (4 x 3, 0.5-mm pitch, 0.238-mm bump height) notes (unless otherwise specified): 1. bump is lead free sn/ag/cu. 2. non-solder mask defined copper landing pad. 3. laser mark on silicon die back; back-lapped, no coating. shown is not actual marking; sample only. index-bump a1 note 3 top side (die back) xxx 3535 recommended land pattern 0.5 0.5 10 0.150
0.229 note 2 solder mask
pad diameter +0.1 bump note 1 321 a b e d a a 2 a 1 s s e silicon c 4 b diameter e e e e millimeters* inches dim min max min max a 0.688 0.753 0.0271 0.0296 a 1 0.218 0.258 0.0086 0.0102 a 2 0.470 0.495 0.0185 0.0195 b 0.306 0.346 0.0120 0.0136 d 1.980 2.020 0.0780 0.0795 e 1.480 1.520 0.0583 0.0598 e 0.5 basic 0.0197 basic s 0.230 0.270 0.0091 0.0106 * use millimeters as the primary measurement. vishay siliconix maintains worldw ide manufacturing c apability. pr oducts may be manufactured at on e of several qualified locati ons. reliability data for silicon technology and package reliability repr esent a composite of all qualified locations. for re lated documents such as package/tape drawings, par t marking, and reliability data, see http://www.vishay.com/ppg?72961 .
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